1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising at least two independent substrates of the same one polarity and at least one substrate of another different polarity and, more particularly, to a technology for reductions in area and power consumption.
2. Description of the Prior Art
In a semiconductor integrated circuit, the substrate potential of a MOS element (MOS transistor) is used occasionally under control. This is because, by changing the substrate potential of the MOS element, an advantageous feature is provided that the threshold and saturation current characteristic of the MOS element can be varied. As an example of making use of the advantageous feature, there is a method which allows the threshold and saturation current characteristic to be varied when the semiconductor integrated circuit is operating and when it comes to a halt. Specifically, there is a method which reduces the difference between the substrate potential of the MOS element and the source potential thereof to 0 when the semiconductor integrated circuit is operating and increases the difference therebetween when the semiconductor integrated circuit comes to a halt, thereby increasing the threshold of the MOS to a level higher than during operation, reducing a sub-threshold leakage current in the MOS element, and achieving lower power consumption. There is also a method which performs variable control of the substrate potential to keep uniform the fluctuations of MOS characteristics due to variations in ambient temperature and internal voltage or variations in fabrication process and maintain circuit performance. To implement the control of the substrate potential of the MOS element described above, a layout method which provides the semiconductor integrated circuit with a higher area efficiency has been proposed (T. Kuroda et. al., “A High-Speed Low-Power 0.3 μm CMOS Gate Array with Variable Threshold Voltage Scheme,” IEEE Custom Integrated Circuit Conference 1996 pp. 53-56).
In the 0.5-μm to 0.3-μm generation in which the above-mentioned technology was proposed, not only a power source voltage but also the threshold voltage of the MOS element followed an ideal scaling rule for a CMOS process with the increasing miniaturization of the process. However, in the recent 0.13-μm to 90-nm generation, a situation has been encountered in which the power source voltage and the threshold voltage of a MOS element cannot follow the ideal scaling rule for the process. That is, even when process scaling is performed, the power source voltage and the threshold voltage remain constant.
One reason for this is that, in the current situation, it is difficult to ensure the stability of a specified circuit composing the semiconductor integrated circuit. In a dynamic circuit or domino circuit having a circuit structure in which an input signal is connected only to MOS transistors of one polarity, a voltage noise margin for the input signal is equal to the threshold of each of the MOS transistor. That is, when the threshold is scaled with the process, the input noise margin consequently lowers. For example, the noise margin of a 90-nm CMOS is about 300 mV at a room temperature (27° C.). As the temperature is higher, the threshold thereof particularly lowers so that the noise margin is about 100 mV at 125° C. When a consideration is given to variations in the power voltage (about 100 mV or more) of the semiconductor integrated circuit, there is substantially no noise margin and, in such a situation, a faulty operation may occur anytime. One approach to solving a problem as described above has been proposed recently. This is a method which gives a substrate potential in accordance with a circuit structure to bring the input noise margin to the same level at a room temperature and thereby maintains a high-speed property (see M. Sumita et al., “Mixed Body-Bias Techniques with fixed Vt and Ids Generation Circuits,” ISSCC Dig. Tech. Papers, pp. 158-159, February 2004). In the approach, substrates having the same polarity and different substrate potentials are needed. FIG. 7 shows a dynamic circuit diagram proposed in the approach. In FIG. 7, each of D1 and D2 denotes input data, CLK denotes a clock signal, and OUT denotes an output from the dynamic circuit. The substrate voltages of individual MOS transistors are connected to VBN1, VBN2, and VBP1, of which the VBN1 and VBN2 are controlled to have different substrate potential characteristics. FIG. 8 shows a drawing obtained as a result of implementing the dynamic circuit of FIG. 7 in accordance with the conventionally proposed layout method (see Japanese Patent Publication No. 3212915). In FIG. 8, each of the elements comprises: NMOS substrates PWELL1 and PWELL2; a PMOS substrate NWELL; polysilicon 2 composing the respective gates of the MOS transistors; S/D diffused layers 1 forming the source/drain of each of the MOS transistors; an inversion diffused layer 3 for supplying a potential to each of the substrates; and contacts 4 providing connection between a first metal layer as the lowermost metal layer and each of the inversion diffused layer 3, the diffused layers 1, and the gates 2. Upper metal layers provided over the first metal layer are normally used for connection between the inputs and outputs of individual circuits, power sources, and substrate wiring, though the depiction thereof is omitted for the avoidance of complicated illustration. The inversion diffused layer 3 for supplying substrate potentials to the substrates PWELL1 and PWELL2 is connected to the metal layers (substrate potential supply lines PL1X, PL1Y, PL2X, and PL2Y) via the contacts 4. The potentials at the respective substrates PWELL1 and PWELL2 are independent of each other. As can be seen from the drawing, since the substrates PWELL1 and PWELL2 should not be conducted to each other, it is necessary to provide insulation therebetween by using the substrate NWELL1. When the dynamic circuit is physically placed, an overhead of the area occupied by the isolation region (region 100 enclosed in each of the broken rectangles in FIG. 8) has presented a problem.